? Ramp & Dump Hold Discharge
Model PH300 is a high performance, thin film hybrid, peak-hold unit, designed to track and hold the peak of analog input signals with rise times (10% to 90% of Vmax) as short as 250 ns. The unit also has the lowest Droop Rate of the held voltage available and consumes less than 36 mW of power in quiescent mode.
While this unit was designed for use in satellite instrumentation, the following unique characteristics make it equally useful in a broad range of space, laboratory and commercial applications.
Range: 0 to (V+- 1.5V)
Input impedance: >1 k?
Rise time (10% - 90%): 250 ns (min)
Linear Gate Control -Digital
Logic level: TTL
Gate open: HIGH
Gate closed: LOW
Gate turn on/off: 40 ns (60 ns max)
Reset Control- Digital
Ramp slew rate: 5 V/μs to 0.001 V/μs
Ramp control: TTL
Ramp active: LOW
Fast reset: <800 ns (dump mode)
Dump control: TTL
Dump active: LOW
Range-load: >5 k?: 0 to (V+- 1.5 V)(typical)
Output slew rate: 30 V/μs
Droop rate: <100 nV/μs @ 25 °C
<5 μV/μs @ 70 °C
Linearity: ±0.01% (typical)
DC offset: ±2 mV (max)
Output current: Internally limited to15 mA
Digital Peak Detect
Logic level: TTL
Vin > Vout : HIGH
Vin < Vout: LOW
Propagation delay: <500 ns (typical)
Internal: 470 pF ±5%
External: 50 pF - 1000 pF (optional)
Operating: -55 °C to +125 °C
Storage: -55 °C to +150 °C
Hardness: 105rad(Si) (optional withPH300RH only)
Amptek High Reliability
Quiescent power: <36 mW @ -5V/+10V
V+: +5 V to +12 V (absolute maximum 18V)
Vˉ: -5 V to -6 V (absolute maximum (V+- Vˉ) <30 V)
Quiescent I+: <2.4 mA (-55 °C to +125 °C)
Quiescent Iˉ: <2.4 mA (-55 °C to +125 °C)
Vd : +5 V (absolute maximum +7 V)
Quiescent Id : <0.01 mA (-55 °C to +125 °C)
Hermetic, 16 pin hybrid, 600 mil DIP
IN is the analog input of the PH300. This input accepts a positive signal. The input signal should not be driven greater than the positive analog power supply, or less than -0.5 V. Schottky diode input protection is recommended.
V- (-5 V to -6 V)
RCEXT is a node that allows connection of an external hold resistor and hold capacitor.When internal hold components are used, RCEXT is left unconnected.
HRES is the node of the internal hold resistor.
HCAP is the node of the internal hold capacitor. This node is normally connected to HRES and DSCHG.
DSCHG is a node of the current generator used to reset the hold capacitor of the PH300. The RAMP reset current is set by an external current source or an external resistor. This node is in a high impedance state when PH300 is in hold mode. Normally this node is connected to the HCAP node.
ISET is a node of the current mirror that sets the discharge current. This node sinks positive current. The discharge current is twice the current at this node. An external resistor R can be connected between ISET and ground. In this case the reset current is approximately set to: 2*(Vˉ+ 0.6 V)/(R + 500 Ω). Amptek recommends a minimum value of 1 k for the external resistor.
NOTE! To ensure proper PH300 tracking mode operation, a reset current must be set regardless of the reset scheme (RAMP or DUMP) used to discharge the hold capacitor.
DUMP (active low) is a TTL compatible signal used for fast reset of the PH300. This signal must be used only in conjunction with the RAMP signal. The DUMP signal can be active only when RAMP is active. A LOW state of this signal causes the discharge current to peak up to 20 mA, causing fast discharge of the hold capacitor. The duration of the DUMP signal should be keep as short as possible, since the high reset current increases substantially the power consumption of the PH300. A fixed duration of 1μs usually is sufficient to completely reset the built in hold capacitor. The PKDT signal can be used as an indicator for the discharge of the hold capacitor and may provide a function to control the duration of the DUMP signal.
RAMP (active low) is a TTL compatible input that controls the linear discharge of the PH300. When this signal is LOW, the DSCHG node sinks current that resets the hold capacitor. Since the reset current is constant, the output of PH300 decays linearly.
GATE (open high) is a TTL compatible logic input that controls the linear gate of the PH300. When GATE is in an active HIGH state, the linear gate is open and the error amplifier of the PH300 can sense the input signal. When GATE is inactive, the error amplifier input is tied to ground.
PKDT is an TTL output that indicates the state of the PH300. When this signal is LOW, the PH300 is in a hold mode.
Vd (+5 V)
V+(+5 V to +12 V)
COMP is a node for frequency compensation of the PH300 when an external hold capacitor is used. In this case a resistor between 20 and 100 Ω can be used to reduce output signal oscillations. This resistor must be connected between COMP and V+. When the internal hold capacitor is used, COMP must be connected to V+.
OUT is the analog output of the PH300. This output is protected for short circuits to ground or any voltage between ground and the positive analog power supply.WARNING! Shorting this output to any negative voltage may destroy the PH300 circuit.This output can drive capacitive loads up to 50 pf (typical). For higher capacitive loads,use a resistor of 50 to 100 Ω in series with OUT. Range is 0 to (V+- 1.5 V), typical.